TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Data Sheet
June 2002
12 28-Channel Framer Registers (continued)
12.1 Framer Global Register Descriptions
Table 313. FRM_SFGR1, Superframer Global Register 1 (R/W)
Address Bit
Name
Function
Reset Default
0x80000
15
FRM_SW_TRN Superframer Configuration Modes.
0
0 = transport mode.
1 = switching mode.
14:13
FRM_LC_
Line Encoder/Decoder Control.
00
CNTRL[1:0]
00 = line encoder and line decoder blocks are not used in either
the framer Tx or Rx paths. This setting is used in the
following switching modes:
■ STS-3/STS-1/DS3/DS2 to CHI/parallel system bus/SMI.
■ STS-3/STS-1/DS3 to line data rate mode.
01 = line decoder is used in the Rx path and line encoder is
used in the Tx path. This setting is used in the framer-only
switching modes:
■ DS1 to CHI/parallel system bus/SMI channelized.
10 = line decoder is used in the Tx path and line encoder is
used in the Rx path. This setting is used in the following
transport modes:
■ DS1 to DS2/DS3/STS-1/STS-3.
11 = reserved.
12
11
FRM_LOOP_ Loop Timing.
0
1
TIMING
0 = superframer is programmed for normal mode.
1 = superframer is programmed for loop timing; i.e., all
received line clocks are looped back to the correspond-
ing transmit line clocks.
DS1/CEPT Terminal Count.
FRM_DS1_
CEPTN
0 = superframer is programmed for CEPT mode, which has
a maximum of 21 operational links. Links 22 to 28 are
disabled.
1 = superframer is programmed for DS1 mode, which has a
maximum of 28 operational links.
Note: For fewer links or DS1/CEPT mixed modes, use
FRM_TC_EN and FRM_TC[7:0] (Table 318) parame-
ters to select an accurate link count.
10
FRM_PLL_
BYPAS
PLL Bypass.
0
0 = internal PLL is used to generate the line clock in the
transmit path.
1 = the PLL is bypassed. External line clock is required in
this mode.
Reserved. Must write to 0.
9:1
0
RSVD
0
0
FRM_LG_BUF_ HDLC Buffer Mode.
MODE
0 = HDLC channel buffers are configured for 128-byte stor-
age. Up to 64 (32) channels can be supported in the
switching (transport) mode.
1 = HDLC channel buffers are combined for 512-byte stor-
age. Up to 16 (8) channels can be supported in the
switching (transport) mode.
246
Agere Systems Inc.
ETC [ ETC ]
