Proprietary TranSwitch Corporation Information for use Solely by its Customers
L3M
TXC-03452B
DATA SHEET
Transmit Path Overhead Bytes And “O”-bits
The Transmit Path Overhead bytes consist of the J1, B3, C2, G1, F2, H4, Z3 (F3), Z4 (K3), and Z5 (N1) bytes,
where Z3, Z4 and Z5 are ANSI designations. The POH bytes may be individually transmitted from the POH
interface, or from RAM locations written by the microprocessor. When POH2RAM is a 1, the POH interface
byte selected for transmission is written into the common RAM location as transmitted. For example, if EXC2 is
set to 1, the transmit POH interface C2 byte is written into the assigned RAM location, in addition to being
transmitted. If EXC2 is set to 0, the transmitted byte is the value written into the corresponding RAM location by
the microprocessor. When a 0 is written into the POH2RAM control bit, the L3M device disables the capability
of writing any of the selected POH interface bytes into their RAM locations. However, individual bytes may still
be transmitted from either the POH interface or the microprocessor-written RAM location. This feature permits
switching back and forth between a selected POH interface byte or a RAM location for transmission, without
having to re-initialize the RAM location. The following table is a summary of this operation:
POH2RAM
EXbn*
Action
1
1
POH interface byte bn written into RAM, and also transmit-
ted.
0
1
0
POH interface byte bn transmitted, but not written into
RAM. Microprocessor writes RAM value as required.
X
POH RAM value of bn byte transmitted.
* e.g., bn = C2.
The relationship between a transmitted Path Overhead byte and the corresponding RAM location is as follows:
Bits of RAM Location
7
6
5
4
3
2
1
0
Bits of Transmitted POH Byte
1
2
3
4
5
6
7
8
TXC-03452B-MB
Ed. 6, April 2001
- 80 of 96 -
ETC [ ETC ]
