July 2004
AS91L1006BU
PIN
PIN
PIN
TYPE
Stable state
after port/reset
PIN NAME
LSP2_TDI
NUMBER NUMBER
LQFP
DESCRIPTION
FPBGA
IN
44
K7
IEEE1149.1 Test Data In on LSP 2
when PASS_THRU_ENABLE is
HIGH.
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 001.
LSP2_TRST
OUT
37
K5
IEEE1149.1 Test Reset on LSP 2
when PASS_THRU_ENABLE is
HIGH.
Buffered version
of signal present
on primary TRST
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 001.
This pin is tri-stated for all other
combinations.
LSP2_AutoWR
OUT
40
K6
Flash, Memory Auto-Write on LSP 2 Logic '1'
when PASS_THRU_ENABLE is
HIGH.
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 001;
PRIM_AutoWR is routed to output.
This pin is tri-stated for all other
combinations.
LSP2_DE
OUT
OUT
36
49
J5
PASS_THRU Debug Enable Output Logic '1'
on LSP 2.
Active low output when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 001.
This pin is high for all other
combinations.
LSP3_TCK
K9
IEEE1149.1 Test Clock on LSP 3
when PASS_THRU_ENABLE is
HIGH.
Buffered version
of signal present
on primary TCK
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 010.
This pin is tri-stated for all other
combinations.
www.alsc.com
Alliance Semiconductor
2003, 2004 © Copyright Alliance Semiconductor Corporation. All Rights reserved.
12
ETC [ ETC ]
