July 2004
AS91L1006BU
Signal Description
PIN
PIN
PIN
TYPE
Stable state
after port/reset
PIN NAME
NUMBER NUMBER
LQFP
DESCRIPTION
FPBGA
LSP1_TCK
OUT
OUT
OUT
31
H4
IEEE1149.1 Test Clock on LSP 1
when PASS_THRU_ENABLE is
HIGH.
Buffered version
of signal present
on primary TCK
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 000.
This pin is tri-stated for all other
combinations.
IEEE1149.1 Test Mode Select on
LSP 1 when PASS_THRU_ENABLE
is HIGH.
LSP1_TMS
32
J4
Logic '1'
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 000.
This pin is tri-stated for all other
combinations.
IEEE1149.1 Test Data Out on LSP 1 Logic '1'
when PASS_THRU_ENABLE is
HIGH.
LSP1_TDO
35
H5
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 000.
This pin is tri-stated for all other
combinations.
LSP1_TDI
IN
33
29
K4
K3
IEEE1149.1 Test Data In on LSP 1
when PASS_THRU_ENABLE is
HIGH.
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 000.
IEEE1149.1 Test Reset on LSP 1
when PASS_THRU_ENABLE is
HIGH.
LSP1_TRST
OUT
Buffered version
of signal present
on primary TRST
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 000.
This pin is tri-stated for all other
combinations.
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10
ETC [ ETC ]
