July 2004
AS91L1006BU
PIN
PIN
PIN
TYPE
Stable state
after port/reset
PIN NAME
NUMBER NUMBER
LQFP
DESCRIPTION
FPBGA
LSP5_TDO
OUT
67
E8
IEEE1149.1 Test Data Out on LSP 5 Logic '1'
when PASS_THRU_ENABLE is
HIGH.
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 100.
This pin is tri-stated for all other
combinations.
LSP5_TDI
IN
68
72
E7
C9
IEEE1149.1 Test Data In on LSP 5
when PASS_THRU_ENABLE is
HIGH.
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 100.
IEEE1149.1 Test Reset on LSP 5
when PASS_THRU_ENABLE is
HIGH.
LSP5_TRST
OUT
Buffered version
of signal present
on primary TRST
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 100.
This pin is tri-stated for all other
combinations.
LSP5_AutoWR
OUT
71
D8
Flash, Memory Auto-Write on LSP 5 Logic '1'
when PASS_THRU_ENABLE is
HIGH.
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 100;
PRIM_AutoWR is routed to output.
This pin is tri-stated for all other
combinations.
LSP5_DE
75
C10
PASS_THRU Debug Enable Output Logic '1'
on LSP 5.
Active low output when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 100.
This pin is high for all other
combinations.
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16
ETC [ ETC ]
