Z8FMC16100 Series Flash MCU
Product Specification
291
Table 165. eZ8 CPU Instruction Summary (Continued)
Address
Mode
Op
Flags
Assembly
Mnemonic
Code(s)
(Hex)
Fetch
Instr.
Symbolic Operation dst src
C
Z
S
V
D H Cycles Cycles
LDEI dst, src
dst ← src
r ← r + 1
rr ← rr + 1
Ir
Irr
Ir
83
93
— — — — — —
2
2
9
9
Irr
LDWX dst, src dst ← src
LDX dst, src dst ← src
ER ER
ER
Ir ER
IRR
IR IRR
1F E8
84
— — — — — —
— — — — — —
5
3
3
3
3
3
3
3
3
3
3
4
4
3
3
2
4
2
3
4
5
4
4
2
3
4
5
2
2
3
5
8
r
85
R
86
87
r
X(rr)
88
X(rr)
ER
r
r
89
94
ER Ir
IRR
95
R
96
IRR IR
ER ER
ER IM
97
E8
E9
98
LEA dst, X(src) dst ← src + X
r
X(r)
rr X(rr)
RR
— — — — — —
99
MULT dst
NOP
dst[15:0] ←
F4
— — — — — —
— — — — — —
dst[15:8] * dst[7:0]
No operation
0F
1
2
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = unaffected.
X = undefined.
0 = reset to 0.
1 = set to 1.
PS024604-1005
P R E L I M I N A R Y
eZ8 CPU Instruction Set