Z8 Encore!® Motor Control Flash MCUs
Product Specification
290
Table 165. eZ8 CPU Instruction Summary (Continued)
Address
Mode
Op
Flags
Assembly
Mnemonic
Code(s)
(Hex)
Fetch
Instr.
Symbolic Operation dst src
C
Z
S
V
D H Cycles Cycles
JP dst
PC ← dst
DA
IRR
DA
8D
C4
— — — — — —
3
2
3
2
3
2
JP cc, dst
if cc is true
PC ← dst
0D–FD — — — — — —
JR dst
PC ← PC + X
DA
DA
8B
— — — — — —
— — — — — —
2
2
2
2
JR cc, dst
if cc is true
PC ← PC + X
0B–FB
LD dst, rc
dst ← src
r
r
IM
X(r)
r
0C–FC — — — — — —
2
3
3
2
3
3
3
3
2
3
2
2
2
2
2
2
3
4
3
2
4
2
3
3
3
5
9
5
9
9
C7
D7
E3
E4
E5
E6
E7
F3
F5
X(r)
r
Ir
R
R
R
R
IR
IM
IR IM
Ir
IR
r
r
R
Irr
Irr
r
LDC dst, src
dst ← src
C2
C5
D2
C3
D3
— — — — — —
Ir
Irr
Ir
LDCI dst, src
LDE dst, src
dst ← src
r ← r + 1
rr ← rr + 1
Irr
Ir
— — — — — —
— — — — — —
Irr
dst ← src
r
Irr
r
82
92
2
2
5
5
Irr
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = unaffected.
X = undefined.
0 = reset to 0.
1 = set to 1.
PS024604-1005
P R E L I M I N A R Y
eZ8 CPU Instruction Set
ZILOG [ ZILOG, INC. ]
