Z8 Encore!® Motor Control Flash MCUs
Product Specification
288
Table 165. eZ8 CPU Instruction Summary (Continued)
Address
Mode
Op
Flags
Assembly
Mnemonic
Code(s)
(Hex)
Fetch
Instr.
Symbolic Operation dst src
C
Z
S
V
D H Cycles Cycles
BTJNZ bit, src, if src[bit] = 1
r
Ir
r
F6
F7
F6
F7
D4
D6
— — — — — —
— — — — — —
— — — — — —
3
3
3
3
2
3
3
4
3
4
6
3
dst
PC ← PC + X
BTJZ bit, src,
dst
if src[bit] = 0
PC ← PC + X
Ir
CALL dst
SP ← SP – 2
@SP ← PC
PC ← dst
IRR
DA
CCF
C ← ~C
EF
B0
*
— — — — —
1
2
2
2
2
2
2
3
3
3
3
3
3
4
4
4
4
2
2
3
2
3
3
4
3
4
3
4
3
4
3
4
3
4
CLR dst
dst ← 00h
R
IR
R
IR
r
— — — — — —
B1
COM dst
dst ← ~dst
60
—
*
*
*
*
*
0 — —
61
CP dst, src
dst – src
r
A2
*
— —
r
Ir
A3
R
R
R
R
A4
IR
IM
A5
A6
IR IM
A7
CPC dst, src
dst – src – C
r
r
1F A2
1F A3
1F A4
1F A5
1F A6
1F A7
*
*
*
*
— —
r
Ir
R
R
R
R
IR
IM
IR IM
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = unaffected.
X = undefined.
0 = reset to 0.
1 = set to 1.
PS024604-1005
P R E L I M I N A R Y
eZ8 CPU Instruction Set
ZILOG [ ZILOG, INC. ]
