Z8 Encore!® Motor Control Flash MCUs
Product Specification
294
Table 165. eZ8 CPU Instruction Summary (Continued)
Address
Mode
Op
Flags
Assembly
Mnemonic
Code(s)
(Hex)
Fetch
Instr.
Symbolic Operation dst src
C
Z
S
V
D
H
Cycles Cycles
SUB dst, src
dst ← dst – src
r
r
22
23
24
25
26
27
28
29
F0
F1
62
63
64
65
66
67
68
69
72
73
74
75
76
77
*
*
*
*
1
*
2
2
3
3
3
3
4
4
2
2
2
2
3
3
3
3
4
4
2
2
3
3
3
3
3
4
3
4
3
4
3
3
2
3
3
4
3
4
3
4
3
3
3
4
3
4
3
4
r
Ir
R
R
R
R
IR
IM
IR IM
ER ER
ER IM
R
SUBX dst, src
SWAP dst
dst ← dst – src
*
*
*
*
*
*
*
*
1
*
dst[7:4] ↔ dst[3:0]
(NOT dst) AND src
X
X — —
0 — —
IR
TCM dst, src
r
r
—
r
Ir
R
R
R
R
IR
IM
IR IM
ER ER
ER IM
TCMX dst, src (NOT dst) AND src
—
—
*
*
*
*
0 — —
0 — —
TM dst, src
dst AND src
r
r
r
Ir
R
R
R
R
IR
IM
IR IM
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = unaffected.
X = undefined.
0 = reset to 0.
1 = set to 1.
PS024604-1005
P R E L I M I N A R Y
eZ8 CPU Instruction Set
ZILOG [ ZILOG, INC. ]
