Z8FMC16100 Series Flash MCU
Product Specification
295
Table 165. eZ8 CPU Instruction Summary (Continued)
Address
Mode
Op
Flags
Assembly
Mnemonic
Code(s)
(Hex)
Fetch
Instr.
Symbolic Operation dst src
C
Z
S
V
D H Cycles Cycles
TMX dst, src
dst AND src
ER ER
ER IM
78
79
F2
—
*
*
0 — —
4
4
2
3
3
6
TRAP Vector
SP ← SP – 2
@SP ← PC
SP ← SP – 1
@SP ← FLAGS
PC ← @Vector
Vect
or
— — — — — —
WDT
5F
B2
B3
B4
B5
B6
B7
B8
B9
— — — — — —
1
2
2
3
3
3
3
4
4
2
3
4
3
4
3
4
3
3
XOR dst, src
dst ← dst XOR src
r
r
—
—
*
*
*
*
0 — —
r
Ir
R
R
R
R
IR
IM
IR IM
ER ER
ER IM
XORX dst, src dst ← dst XOR src
0 — —
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = unaffected.
X = undefined.
0 = reset to 0.
1 = set to 1.
Flags Register
The Flags Register contains the status information regarding the most recent arithmetic,
logical, bit manipulation or rotate and shift operation. The Flags Register contains six bits
of status information that are set or cleared by CPU operations. Four of the bits (C, V, Z,
and S) can be tested for use with conditional jump instructions. Two flags (H and D) can-
not be tested and are used for Binary-Coded Decimal (BCD) arithmetic.
The two remaining bits, User Flags (F1 and F2), are available as general-purpose status
bits. User Flags are unaffected by arithmetic operations and must be set or cleared by
instructions. The User Flags cannot be used with conditional Jumps. They are undefined at
PS024604-1005
P R E L I M I N A R Y
eZ8 CPU Instruction Set
ZILOG [ ZILOG, INC. ]
