Z8 Encore!® Motor Control Flash MCUs
Product Specification
286
Table 164. Rotate and Shift Instructions (Continued)
Mnemonic
RLC
Operands
dst
Instruction
Rotate Left through Carry
Rotate Right
RR
dst
RRC
dst
Rotate Right through Carry
Shift Right Arithmetic
Shift Right Logical
Swap Nibbles
SRA
dst
SRL
dst
SWAP
dst
eZ8 CPU Instruction Summary
Table 165 summarizes the eZ8 CPU instructions. The table identifies the addressing
modes employed by the instruction, the effect upon the Flags Register, the number of CPU
clock cycles required for the instruction fetch, and the number of CPU clock cycles
required for the instruction execution.
.
Table 165. eZ8 CPU Instruction Summary
Address
Op
Mode
Flags
Assembly
Mnemonic
Code(s)
(Hex)
Fetch
Instr.
Symbolic Operation dst src
C
Z
S
V
D
H
Cycles Cycles
ADC dst, src
dst ← dst + src + C
r
r
12
13
14
15
16
17
18
19
*
*
*
*
0
*
2
2
3
3
3
3
4
4
3
4
3
4
3
4
3
3
r
Ir
R
R
R
R
IR
IM
IR IM
ER ER
ER IM
ADCX dst, src
dst ← dst + src + C
*
*
*
*
0
*
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = unaffected.
X = undefined.
0 = reset to 0.
1 = set to 1.
PS024604-1005
P R E L I M I N A R Y
eZ8 CPU Instruction Set
ZILOG [ ZILOG, INC. ]
