Z8018x Family
MPU User Manual
273
Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine
Cycle
Instruction
States
Address
Data
RD WR MREQ IORQ M1 HALT ST
MC1
MC2
T1T2T3 1st Op Code 1st Op
Address Code
0
0
1
1
1
0
1
1
1
0
0
1
0
0
1
0
0
0
1
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
0
T1T2T3 2nd Op Code 2nd Op
Address
Code
PUSH IX
PUSH IY
MC3~M TiTi
C4
*
Z
MC5
MC6
MC1
T1T2T3 SP-1
IXH
IYH
T1T2T3 SP-2
IXL
IYL
T1T2T3 1st Op Code 1st Op
Address
T1T2T3 SP
T1T2T3 SP+1
Code
RET
MC2
MC3
MC1
DATA
DATA
0
0
0
1
1
1
0
0
0
1
1
1
1
1
0
1
1
1
1
1
0
T1T2T3 1st Op Code 1st Op
RET f
Address
Code
(If condition
is false)
MC2~M TiTi
C3
*
Z
1
0
1
1
1
0
1
1
1
0
1
1
1
0
MC1
T1T2T3 1st Op Code 1st Op
Address
Code
RET f
(If condition
is true)
MC2
MC3
MC4
MC1
Ti
*
Z
1
0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
T1T2T3 SP
DATA
DATA
T1T2T3 SP+1
T1T2T3 1st Op Code 1st Op
Address Code
MC2
T1T2T3 2nd Op Code 2nd Op
0
1
0
1
0
1
1
RETI (R0, R1)
RETN
Address
T1T2T3 SP
T1T2T3 SP+1
Code
MC3
MC4
DATA
DATA
0
0
1
1
0
0
1
1
1
1
0
1
1
1
UM005001-ZMP0400
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