Z8018x Family
MPU User Manual
272
Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine
Instruction
Cycle
States
Address
Data
RD WR MREQ IORQ M1 HALT ST
MC1
T1T2T3 1st Op Code 1st Op
Address Code
0
0
1
1
0
0
1
1
0
0
1
1
0
1
OTIR
MC2
T1T2T3 2nd Op Code 2nd Op
OTDR
(if Br=0)
Address
T1T2T3 HL
T1T2T3 BC
Code
MC3
MC4
MC1
DATA
DATA
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
1
1
1
1
0
T1T2T3 1st Op Code 1st Op
Address
T1T2T3 SP
T1T2T3 SP+1
Code
POP zz
MC2
MC3
MC1
DATA
DATA
0
0
0
1
1
1
0
0
0
1
1
1
1
1
0
1
1
1
1
1
0
T1T2T3 1st Op Code 1st Op
Address Code
POP IX
POP IY
MC2
T1T2T3 2nd Op Code 2nd Op
0
1
0
1
0
1
1
Address
T1T2T3 SP
T1T2T3 SP+1
Code
MC3
MC4
MC1
DATA
DATA
0
0
0
1
1
1
0
0
0
1
1
1
1
1
0
1
1
1
1
1
0
PUSH zz
T1T2T3 1st Op Code 1st Op
Address
Code
MC2
TiTi
*
Z
1
1
1
1
1
1
1
~MC3
MC4
MC5
T1T2T3 SP-1
T1T2T3 SP-2
zzH
zzL
1
1
0
0
0
0
1
1
1
1
1
1
1
1
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