Z8018x Family
MPU User Manual
276
Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine
Instruction
Cycle
States
Address
Data
RD WR MREQ IORQ M1 HALT ST
MC1
T1T2T3 1st Op Code 1st Op
0
1
1
1
0
1
1
1
0
1
1
1
0
1
Address
*
Code
Z
MC2
TiTi
RST v
~MC3
MC4
MC5
MC1
T1T2T3 SP-1
T1T2T3 SP-2
PCH
PCL
1
1
0
0
0
1
0
0
0
1
1
1
1
1
0
1
1
1
1
1
0
SCF
T1T2T3 1st Op Code 1st Op
Address Code
MC1
MC2
T1T2T3 1st Op Code 1st Op
Address Code
0
0
1
1
0
0
1
1
0
0
1
1
0
1
SET b,g
RES b,g
T1T2T3 2nd Op Code 2nd Op
Address
Code
MC3
MC1
Ti
*
Z
1
0
1
1
1
0
1
1
1
0
1
1
1
0
T1T2T3 1st Op Code 1st Op
Address Code
MC2
T1T2T3 2nd Op Code 2ndOp
0
1
0
1
0
1
1
SET b. (HL)
RES b, (HL)
Address
T1T2T3 HL
Ti
T1T2T3 HL
Code
DATA
Z
MC3
MC4
MC5
0
1
1
1
1
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
*
DATA
UM005001-ZMP0400
ZILOG [ ZILOG, INC. ]
