Z8018x Family
MPU User Manual
271
Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine
Cycle
Instruction
States
Address
Data
RD WR MREQ IORQ M1 HALT ST
MC1
MC2
T1T2T3 1st Op Code 1st Op
Address Code
0
0
1
1
0
0
1
1
0
0
1
1
0
1
T1T2T3 2nd Op Code 2nd Op
Address
Code
OTIMR**
OTDMR**
(if Br= 0)
MC3
MC4
MC5
Ti
*
Z
1
0
1
1
1
0
1
0
1
1
1
0
1
1
1
1
1
1
1
1
1
T1T2T3 HL
DATA
DATA
T1T2T3 C to A0~A7
00H to
A8~A15
MC6
MC1
Ti
*
Z
1
0
1
1
1
0
1
1
1
0
1
1
1
0
T1T2T3 1st Op Code 1st Op
Address Code
OUTI
OUTD
MC2
T1T2T3 2nd Op Code 2nd Op
0
1
0
1
0
1
1
Address
T1T2T3 HL
T1T2T3 BC
Code
MC3
MC4
MC1
DATA
DATA
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
1
1
1
1
0
T1T2T3 1st Op Code 1st Op
Address Code
MC2
T1T2T3 2nd Op Code 2nd Op
0
1
0
1
0
1
1
OTIR
OTDR
(If Br`¹ 0)
Address
T1T2T3 HL
T1T2T3 BC
Code
DATA
DATA
Z
MC3
MC4
0
1
1
1
0
1
0
1
1
1
0
1
1
1
1
1
1
1
1
1
1
MC5~M TiTi
C6
*
UM005001-ZMP0400
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