Z8018x Family
MPU User Manual
275
Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine
Cycle
Instruction
States
Address
Data
RD WR MREQ IORQ M1 HALT ST
MC1
MC2
T1T2T3 1st Op Code 1st Op
Address Code
0
0
1
1
0
0
1
1
0
0
1
1
0
1
RLC (HL)
RL (HL)
RRC (HL)
RR (HL)
SLA (HL)
SRA (HL)
SRL (HL)
T1T2T3 2nd Op Code 2nd Op
Address
T1T2T3 HL
Ti
T1T2T3 HL
Code
DATA
Z
MC3
MC4
MC5
MC1
0
1
1
0
1
1
0
1
0
1
0
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
*
DATA
RLC (IX + d)
RLC (IY + d)
RL (IX + d)
T1T2T3 1st Op Code 1st Op
Address Code
MC2
MC3
MC4
MC5
T1T2T3 2nd Op Code 2ndOp
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
1
1
1
1
1
1
1
1
1
RL (IY + d)
RRC (IX + d)
RRC (IY + d)
RR (IX + d)
RR (IY + d)
SLA (IX + d)
SLA (IY + d)
SRA (IX + d)
SRA (IY + d)
SRL (IX + d)
SRL (IY + d)
Address
Code
T1T2T3 1st operand
Address
d
T1T2T3 3rd Op Code 3rd Op
Address
Code
T1T2T3 IX+d
DATA
IY+d
*
MC6
MC7
Ti
Z
1
1
1
0
1
0
1
1
1
1
1
1
1
1
T1T2T3 IX+d
IY+d
DATA
MC1
MC2
MC3
T1T2T3 1st Op Code 1st Op
Address Code
0
0
1
1
0
0
1
1
0
0
1
1
0
1
T1T2T3 2nd Op Code 2nd Op
Address
Code
DATA
Z
RLD
RRD
T1T2T3 HL
0
1
1
1
0
1
1
1
1
1
1
1
1
1
MC4~M TiTiTiTi
C7
*
MC8
T1T2T3 HL
DATA
1
0
0
1
1
1
1
UM005001-ZMP0400
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