Z8018x Family
MPU User Manual
274
Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine
Instruction
Cycle
States
Address
Data
RD WR MREQ IORQ M1 HALT ST
MC1
T1T2T3 1st Op Code 1st Op
Address Code
0
0
1
0
1
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
0
1
0
0
0
0
1
1
1
1
1
1
1
1
1
0*5
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
MC2
T1T2T3 2nd Op Code 2nd Op
0*5
1
Address
Code
MC3
~MC5
TiTiTi
*
Z
1*5
1
MC6
MC7
MC8
MC9
MC10
MC1
T1T2T3 1st Op Code 1st Op
0*5
0
Address
Code
RETI (Z)
Ti
*
Z
1*5
1
T1T2T3 2nd Op Code 2nd Op
0*5
0
Address
Code
T1T2T3 SP
data
1*5
1
T1T2T3 SP+1
data
1*5
1
RLCA
RLA
RRCA
RRA
T1T2T3 1st Op Code 1st Op
Address Code
0
RLC g
RL g
MC1
MC2
MC3
T1T2T3 1st Op Code 1st Op
Address Code
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
1
1
RRC g
RR g
SLA g
SRA g
SRL g
T1T2T3 2nd Op Code 2nd Op
Address
Code
Ti
*
Z
*5 The upper and lower data show the state of M1 when IOC = 1 and IOC = 0 respectively.
UM005001-ZMP0400
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