Z8018x Family
MPU User Manual
269
Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine
Cycle
Instruction
States
Address
Data
RD WR MREQ IORQ M1 HALT ST
MC1
MC2
T1T2T3 1st Op Code 1st Op
0
0
1
1
0
0
1
1
0
1
1
1
0
1
Address
Code
m
T1T2T3 1st operand
Address
OUT (m),A
MC3
MC4
Ti
*
Z
1
1
1
0
1
1
1
0
1
1
1
1
1
1
T1T2T3 m to A0~A7
A to A8~A15
A
MC1
MC2
T1T2T3 1st Op Code 1st Op
Address Code
0
0
1
1
0
0
1
1
0
0
1
1
0
1
T1T2T3 2nd Op Code 2nd Op
OUT (C),g
Address
Code
MC3
MC4
MC1
Ti
*
Z
g
1
1
0
1
0
1
1
1
0
1
0
1
1
1
0
1
1
1
1
1
0
T1T2T3 BC
T1T2T3 1st Op Code 1st Op
Address Code
MC2
MC3
T1T2T3 2nd Op Code 2nd Op
0
0
1
1
0
0
1
1
0
1
1
1
1
1
Address
Code
OUT0 (m),g**
T1T2T3 1st operand
Address
m
MC4
MC5
Ti
*
Z
g
1
1
1
0
1
1
1
0
1
1
1
1
1
1
T1T2T3 m to A0~A7
00H to
A8~A15
UM005001-ZMP0400
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