Z8018x Family
MPU User Manual
277
Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine
Cycle
Instruction
States
Address
Data
RD WR MREQ IORQ M1 HALT ST
MC1
MC2
MC3
MC4
MC5
T1T2T3 1st Op Code 1st Op
Address Code
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
1
0
1
1
1
1
1
1
0
1
1
1
1
T1T2T3 2nd Op Code 2nd Op
Address
Code
SET b, (IX+d)
SET b, (IY+d)
RES b, (IX+d)
RES b, (IY+d)
T1T2T3 1st operand
Address
d
T1T2T3 3rd Op Code 3rd Op
Address
Code
T1T2T3 IX+d
DATA
IY+d
*
MC6
MC7
Ti
Z
1
1
1
0
1
0
1
1
1
1
1
1
1
1
T1T2T3 IX+ d
IY+d
DATA
MC1
MC2
T1T2T3 1st Op Code 1stOp
Address Code
0
0
1
1
0
0
1
1
0
0
1
1
0
1
SLP**
T1T2T3 2nd Op Code 2nd Op
Address
Code
—
—
7FFFFH
Z
1
0
1
1
1
0
1
1
1
0
0
1
1
0
MC1
T1T2T3 1st Op Code 1st Op
Address Code
MC2
MC3
MC4
T1T2T3 2nd Op Code 2nd Op
0
0
0
1
1
1
0
0
1
1
1
0
0
1
1
1
1
1
1
1
1
Address
Code
TSTIO m**
T1T2T3 1st operand
Address
m
T1T2T3 C to A0~A7
00H to
DATA
A8~A15
UM005001-ZMP0400
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