Z8018x Family
MPU User Manual
268
Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine
Instruction
Cycle
States
Address
Data
RD WR MREQ IORQ M1 HALT ST
MC1
T1T2T3 1st Op Code 1st Op
Address Code
0
0
1
1
0
0
1
1
0
0
1
1
0
1
MC2
T1T2T3 2nd Op Code 2nd Op
LDIR
LDDR
(If BCR¹ 0)
Address
T1T2T3 HL
T1T2T3 DE
Code
DATA
DATA
Z
MC3
MC4
0
1
1
1
0
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
MC5~M TiTi
C6
*
MC1
T1T2T3 1st Op Code 1st Op
Address Code
0
0
1
1
0
0
1
1
0
0
1
1
0
1
LDIR
MC2
T1T2T3 2nd Op Code 2nd Op
LDDR
(If BCR=0)
Address
T1T2T3 HL
T1T2T3 DE
Code
MC3
MC4
MC1
DATA
DATA
0
1
0
1
0
1
0
0
0
1
1
1
1
1
0
1
1
1
1
1
0
T1T2T3 1st Op Code 1st Op
Address Code
MC2
MC3
T1T2T3 2nd Op Code 2nd Op
0
1
1
1
0
1
1
1
0
1
1
1
1
1
MLT ww**
Address
Code
TiTiTTi
*
Z
~MC13 TiTiTiTi
TiTiTi
MC1
MC2
MC1
T1T2T3 1st Op Code 1st Op
Address Code
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
1
0
NEG
NOP
T1T2T3 2nd Op Code 2nd Op
Address Code
T1T2T3 1st Op Code 1st Op
Address Code
UM005001-ZMP0400
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