Z8018x Family
MPU User Manual
261
Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine
Cycle
Instruction
States
Address
Data
RD WR MREQ IORQ M1 HALT ST
MC1
MC2
T1T2T3 1st Op Code 1st Op
0
0
1
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
1
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
0
1
1
0
1
0
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
0
1
0
1
1
0
Address
Code
j-2
T1T2T3 1st operand
Address
JR j
MC3~M TiTi
C4
*
Z
JR C,j JR NC,j
JR Z,j JR NZ,j
(if condition
is false)
MC1
MC2
MC1
MC2
T1T2T3 1st Op Code 1st Op
Address
Code
T1T2T3 1st operand
Address
j-2
T1T2T3 1st Op Code 1st Op
JR C,j JR NC,j
JR Z,j JR NZ,j
(if condition
is true)
Address
Code
T1T2T3 1st operand
Address
j-2
MC3~M TiTi
C4
*
Z
MC1
T1T2T3 1st Op Code 1st Op
LD g,g'
Address
Code
MC2
MC1
Ti
*
Z
1
0
1
1
1
0
1
1
1
0
1
1
1
0
T1T2T3 1st Op Code 1st Op
Address
Code
LD g,m
MC2
MC1
MC2
T1T2T3 1st operand
Address
m
0
0
0
1
1
1
0
0
0
1
1
1
1
0
1
1
1
1
1
0
1
T1T2T3 1st Op Code 1st Op
LD g, (HL)
Address
Code
T1T2T3 HL
DATA
UM005001-ZMP0400
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