Z8018x Family
MPU User Manual
257
Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine
Cycle
Instruction
States
Address
Data
RD WR MREQ IORQ M1 HALT ST
MC1
MC2
T1T2T3 1st Op Code 1st Op
Address Code
0
0
1
1
0
0
1
1
0
0
1
1
0
1
T1T2T3 2nd Op Code 2nd Op
EX (SP),IX
EX (SP),IY
Address
T1T2T3 SP
T1T2T3 SP+1
Ti
Code
DATA
DATA
Z
MC3
MC4
MC5
MC6
0
0
1
1
1
1
1
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
*
T1T2T3 SP+1
IXH
IYH
MC7
MC1
—
T1T2T3 SP
IXL
IYL
1
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
1
1
0
1
1
1
1
0
0
0
1
0
T1T2T3 1st Op Code 1st Op
Address Code
HALT
—
Next Op Code Next Op
Address Code
IM0
IM1
IM2
MC1
MC2
MC1
T1T2T3 1st Op Code 1st Op
Address Code
T1T2T3 2nd Op Code 2nd Op
Address Code
T1T2T3 1st Op Code 1st Op
INC g
Address
Code
DEC g
MC2
MC1
Ti
*
Z
1
0
1
1
1
0
1
1
1
0
1
1
1
0
T1T2T3 1st Op Code 1st Op
Address
T1T2T3 HL
Ti
T1T2T3 HL
Code
DATA
Z
INC (HL)
DEC (HL)
MC2
MC3
MC4
0
1
1
1
1
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
*
DATA
UM005001-ZMP0400
ZILOG [ ZILOG, INC. ]
