Z8018x Family
MPU User Manual
258
Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine
Instruction
Cycle
States
Address
Data
RD WR MREQ IORQ M1 HALT ST
MC1
T1T2T3 1st Op Code 1st Op
Address Code
0
0
0
1
0
1
1
1
1
1
0
0
0
1
0
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
MC2
MC3
T1T2T3 2nd Op Code 2nd Op
INC (IX+ d)
INC (IY+d)
Address
Code
T1T2T3 1st operand
Address
d
MC4~M TiTi
C5
*
Z
DEC (IX+d)
DEC (IY+d)
MC6
T1T2T3 X+ d
IY+ d
DATA
MC7
MC8
T1
*
Z
1
1
1
0
1
0
1
1
1
1
1
1
1
1
T1T2T3 IX+ d
IY+d
DATA
MC1
T1T2T3 1st Op Code 1st Op
0
1
0
1
0
1
0
INC ww
DEC ww
Address
Code
MC2
MC1
Ti
*
Z
1
0
1
1
t
1
1
1
0
1
1
1
0
T1T2T3 1st Op Code 1st Op
Address Code
0
INC IX
INC IY
DEC IX
DEC IY
MC2
T1T2T3 2nd Op Code 2nd Op
0
1
0
1
0
1
1
Address
Code
MC3
MC1
Ti
*
Z
1
0
1
1
1
0
1
1
1
0
1
1
1
0
T1T2T3 1st Op Code 1st Op
Address
Code
MC2
MC3
T1T2T3 1st operand
Address
m
0
0
1
1
0
1
1
0
1
1
1
1
1
1
IN A,(m)
T1T2T3 m to A0~A7 DATA
A to A8~A15
UM005001-ZMP0400
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