Z8018x Family
MPU User Manual
265
Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine
Cycle
Instruction
States
Address
Data
RD WR MREQ IORQ M1 HALT ST
MC1
MC2
MC3
T1T2T3 1st Op Code 1st Op
0
0
0
1
1
1
0
0
0
1
1
1
0
1
1
1
1
1
0
1
1
Address
Code
n
T1T2T3 1st operand
Address
LD HL, (mn)
T1T2T3 2nd operand
Address
m
MC4
MC5
MC1
T1T2T3 mn
DATA
DATA
0
0
0
1
1
1
0
0
0
1
1
1
1
1
0
1
1
1
1
1
0
T1T2T3 mn+1
T1T2T3 1st Op Code 1st Op
Address Code
MC2
MC3
MC4
T1T2T3 2nd Op Code 2nd Op
0
0
0
1
1
1
0
0
0
1
1
1
0
1
1
1
1
1
1
1
1
Address
Code
LD ww,(mn)
T1T2T3 1st operand
Address
n
T1T2T3 2nd operand
Address
m
MC5
MC6
MC1
T1T2T3 mn
DATA
DATA
0
0
0
1
1
1
0
0
0
1
1
1
1
1
0
1
1
1
1
1
0
T1T2T3 mn+ 1
T1T2T3 1st Op Code 1st Op
Address Code
MC2
MC3
MC4
T1T2T3 2nd Op Code 2nd Op
0
0
0
1
1
1
0
0
0
1
1
1
0
1
1
1
1
1
1
1
1
Address
Code
LD IX,(mn)
LD IY,(mn)
T1T2T3 1st operand
Address
n
T1T2T3 2nd operand
Address
m
MC5
MC6
T1T2T3 mn
DATA
DATA
0
0
1
1
0
0
1
1
1
1
1
1
1
1
T1T2T3 mn+1
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