Z8018x Family
MPU User Manual
263
Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine
Cycle
Instruction
States
Address
Data
RD WR MREQ IORQ M1 HALT ST
MC1
MC2
MC3
MC4
MC5
MC1
MC2
MC1
MC2
MC3
T1T2T3 1st Op Code 1st Op
Address Code
0
0
0
0
1
0
0
0
0
0
1
1
1
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
1
0
1
1
T1T2T3 2nd Op Code 2nd Op
Address
Code
LD (IX+d),m
LD (IY+d),m
T1T2T3 1st operand
Address
d
T1T2T3 2nd operand
Address
m
T1T2T3 IX+ d
IY+d
DATA
T1T2T3 1st Op Code 1st Op
LD A, (BC)
LD A, (DE)
Address
Code
T1T2T3 BC
DATA
DE
T1T2T3 1st Op Code 1st Op
Address
Code
n
T1T2T3 1st operand
Address
LD A,(mn)
T1T2T3 2nd operand
Address
m
MC4
MC1
T1T2T3 mn
DATA
0
0
1
1
0
0
1
1
1
0
1
1
1
0
T1T2T3 1st Op Code 1st Op
Address
Code
LD (BC),A
LD (DE),A
MC2
MC3
Ti
*
Z
1
1
1
0
1
0
1
1
1
1
1
1
1
1
T1T2T3 BC
DE
A
UM005001-ZMP0400
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