Z8018x Family
MPU User Manual
262
Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine
Instruction
Cycle
States
Address
Data
RD WR MREQ IORQ M1 HALT ST
MC1
T1T2T3 1st Op Code 1st Op
Address Code
0
0
0
1
0
0
1
1
1
1
1
1
0
0
0
1
0
0
1
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
0
MC2
MC3
T1T2T3 2nd Op Code 2nd Op
Address
Code
LD g, (IX+d)
LD g, (IY+d)
T1T2T3 1st operand
Address
d
MC4~M TiTi
C5
*
Z
MC6
T1T2T3 IX+d
IY+d
DATA
MC1
T1T2T3 1st Op Code 1st Op
Address
Code
LD (HL),g
MC2
MC3
MC1
Ti
*
Z
g
1
1
0
1
0
1
1
0
0
1
1
1
1
1
0
1
1
1
1
1
0
T1T2T3 HL
T1T2T3 1st Op Code 1st Op
Address Code
MC2
MC3
T1T2T3 2nd Op Code 2nd Op
0
0
1
1
0
0
1
1
1
1
0
1
1
0
0
0
1
0
0
0
0
1
1
1
1
1
1
1
0
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
Address
Code
LD (IX + d),g
LD (IY + d),g
T1T2T3 1st operand
Address
d
MC4~
MC6
TiTiTi
*
Z
g
MC7
MC1
MC2
MC3
T1T2T3 IX+d
IY+d
T1T2T3 1st Op Code 1st Op
Address
Code
LD (HL),m
T1T2T3 1st operand
Address
m
T1T2T3 HL
DATA
UM005001-ZMP0400
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