Z8018x Family
MPU User Manual
260
Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine
Instruction
Cycle
States
Address
Data
RD WR MREQ IORQ M1 HALT ST
MC1
T1T2T3 1st Op Code 1st Op
Address Code
0
0
1
1
0
0
1
1
0
0
1
1
0
1
INIR
MC2
T1T2T3 2nd Op Code 2nd Op
INDR
(If Br=0)
Address
T1T2T3 BC
T1T2T3 HL
Code
MC3
MC4
MC1
DATA
DATA
0
1
0
1
0
1
1
0
0
0
1
1
1
1
0
1
1
1
1
1
0
T1T2T3 1st Op Code 1st Op
Address
Code
MC2
MC3
MC1
MC2
MC1
MC2
MC3
MC1
MC1
MC2
T1T2T3 1st operand
Address
n
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
1
0
0
1
JP mn
T1T2T3 2nd operand
Address
m
T1T2T3 1st Op Code 1st Op
JP f,mn
(if is false)
Address
Code
T1T2T3 1st operand
Address
n
T1T2T3 1st Op Code 1st Op
Address
Code
JP f,mn
(If f is true)
T1T2T3 1st operand
Address
n
T1T2T3 2nd operand
Address
m
JP (HL)
T1T2T3 1st Op Code 1st Op
Address Code
T1T2T3 1st Op Code 1st Op
Address Code
JP (IX)
JP (IY)
T1T2T3 2nd Op Code 2nd Op
Address Code
UM005001-ZMP0400
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