Z8018x Family
MPU User Manual
259
Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine
Cycle
Instruction
States
Address
Data
RD WR MREQ IORQ M1 HALT ST
MC1
MC2
T1T2T3 1st Op Code 1st Op
Address Code
0
0
1
1
0
0
1
1
0
0
1
1
0
1
T1T2T3 2nd Op Code 2nd Op
IN g,(C)
Address
Code
MC3
MC1
T1T2T3 BC
DATA
0
0
1
1
1
0
0
1
1
0
1
1
1
0
T1T2T3 1st Op Code 1st Op
Address Code
MC2
MC3
MC4
T1T2T3 2nd Op Code 2nd Op
0
0
0
1
1
1
0
0
1
1
1
0
0
1
1
1
1
1
1
1
1
Address
Code
INO g,(m)**
T1T2T3 1st operand
Address
m
T1T2T3 m to A0~A7 DATA
00H to
A8~A15
MC1
MC2
T1T2T3 1st Op Code 1st Op
0
0
1
1
0
0
1
1
0
0
1
1
0
1
Address
Code
T1T2T3 2nd Op Code 2nd Op
INI
IND
Address
T1T2T3 BC
T1T2T3 HL
Code
MC3
MC4
MC1
DATA
DATA
0
1
0
1
0
1
1
0
0
0
1
1
1
1
0
1
1
1
1
1
0
T1T2T3 1st Op Code 1st Op
Address Code
MC2
T1T2T3 2nd Op Code 2nd Op
0
1
0
1
0
1
1
Address
T1T2T3 BC
T1T2T3 HL
Code
DATA
DATA
Z
INIR
INDR
(If Br¹ 0)
MC3
MC4
0
1
1
1
0
1
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
MC5~M TiTi
C6
*
UM005001-ZMP0400
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