Z8018x Family
MPU User Manual
264
Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine
Instruction
Cycle
States
Address
Data
RD WR MREQ IORQ M1 HALT ST
MC1
T1T2T3 1st Op Code 1st Op
0
0
0
1
1
1
0
0
0
1
1
1
0
1
1
1
1
1
0
1
1
Address
Code
n
MC2
MC3
T1T2T3 1st operand
Address
LD (mn),A
T1T2T3 2nd operand
Address
m
MC4
MC5
MC1
Ti
*
Z
1
1
0
1
0
1
1
0
0
1
1
1
1
1
0
1
1
1
1
1
0
T1T2T3 mn
A
LD A,I
T1T2T3 1st Op Code 1st Op
Address Code
*4
LD A,R
LD I,A
LD R,A
MC2
MC1
MC2
MC3
MC1
MC2
MC3
MC4
T1T2T3 2nd Op Code 2nd Op
Address Code
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
1
1
1
T1T2T3 1st Op Code 1st Op
Address
Code
LD ww, mn
T1T2T3 1st operand
Address
n
T1T2T3 2nd operand
Address
m
T1T2T3 1st Op Code 1st Op
Address Code
T1T2T3 2nd Op Code 2nd Op
LD IX,mn
LD IY,mn
Address
Code
T1T2T3 1st operand
Address
n
T1T2T3 2nd operand
Address
m
*4 In the case of R1 and Z MASK, interrupt request is not sampled.
UM005001-ZMP0400
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