Z8018x Family
MPU User Manual
256
Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine
Instruction
Cycle
States
Address
Data
RD WR MREQ IORQ M1 HALT ST
MC1
T1T2T3 1st Op Code 1st Op
0
1
0
1
0
1
0
Address
*
Code
Z
DJNZ j
(If Br ¹ 0)
MC2
MC3
Ti*2
1
0
1
1
1
0
1
1
1
1
1
1
1
1
T1T2T3 1st operand
Address
j-2
MC4~M TiTi
C5
*
Z
1
0
1
1
1
0
1
1
1
0
1
1
1
0
MC1
T1T2T3 1st Op Code 1st Op
Address
Code
DJNZ j
(If Br=0)
MC2
MC3
Ti*1
*
Z
1
0
1
1
1
0
1
1
1
1
1
1
1
1
T1T2T3 1st operand
Address
j-2
EI*3
MC1
MC1
MC1
T1T2T3 1st Op Code 1st Op
Address Code
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
EX DE, HL
EXX
T1T2T3 1st Op Code 1st Op
Address Code
T1T2T3 1st Op Code 1st
EX AF, AF’
Address
Op Code
MC2
MC1
Ti
*
Z
1
0
1
1
1
0
1
1
1
0
1
1
1
0
T1T2T3 1st Op Code 1st Op
Address
T1T2T3 SP
T1T2T3 SP+1
Ti
Code
DATA
DATA
Z
MC2
MC3
MC4
MC5
MC6
0
0
1
1
1
1
1
1
0
0
0
0
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
EX (SP), HL
*
T1T2T3 SP+1
T1T2T3 SP
H
L
*2 DMA,REFRESH, or BUS RELEASE cannot be executed after this state. (Request is ignored)
*3 Interrupt request is not sampled.
UM005001-ZMP0400
ZILOG [ ZILOG, INC. ]
