Z8018x Family
MPU User Manual
255
Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine
Cycle
Instruction
States
Address
Data
RD WR MREQ IORQ M1 HALT ST
MC1
MC2
MC3
T1T2T3 1st Op Code 1st Op
Address Code
0
0
1
1
0
0
1
1
0
0
1
1
0
1
T1T2T3 2nd Op Code 2nd Op
CPI
CPD
Address
T1T2T3 HL
TiTiTi
Code
DATA
Z
0
1
1
1
0
1
1
1
1
1
1
1
1
1
MC4
*
~MC6
MC1
MC2
MC3
T1T2T3 1st Op Code 1st Op
Address Code
0
0
1
1
0
0
1
1
0
0
1
1
0
1
CPIR
CPDR
(If BCR ¹ 0 and
Ar = (HL)M
T1T2T3 2nd Op Code 2nd Op
Address
Code
DATA
Z
)
T1T2T3 HL
0
1
1
1
0
1
1
1
1
1
1
1
1
1
MC4~M TiTiTi
*
C8
TiTi
MC1
T1T2T3 1st Op Code 1st Op
0
0
1
1
0
0
1
1
0
0
1
1
0
1
Address Code
CPIR
CPDR
(If BCR=0 or
MC2
MC3
T1T2T3 2nd Op Code 2nd Op
Address
Code
DATA
Z
Ar=(HL)M
)
T1T2T3 HL
0
1
1
1
0
1
1
1
1
1
1
1
1
1
MC4~M TiTiTi
C6
*
CPL
MC1
T1T2T3 1st Op Code 1st Op
Address Code
0
0
1
1
0
0
1
1
0
0
1
1
0
0
MC1
T1T2T3 1st Op Code 1st Op
DAA
DI*1
Address
Code
MC2
MC1
Ti
*
Z
1
0
1
1
1
0
1
1
1
0
1
1
1
0
T1T2T3 1st Op Code 1st Op
Address Code
* 1 Interrupt request is not sampled.
UM005001-ZMP0400
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