Z8018x Family
MPU User Manual
254
Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine
Instruction
Cycle
States
Address
Data
RD WR MREQ IORQ M1 HALT ST
MC1
T1T2T3 1st Op Code 1st Op
0
0
0
1
1
1
0
0
0
1
1
1
0
1
1
1
1
1
0
1
1
Address
Code
n
MC2
MC3
T1T2T3 1st operand
Address
CALL mn
T1T2T3 2nd operand
Address
m
MC4
MC5
MC6
MC1
Ti
*
Z
1
1
1
0
1
0
0
1
1
0
0
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
T1T2T3 SP-1
T1T2T3 SP-2
PCH
PCL
CALL f,mn (If
T1T2T3 1st Op Code 1st Op
condition is false)
Address
Code
MC2
MC1
MC2
MC3
T1T2T3 1st operand
Address
n
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
T1T2T3 1st Op Code 1st Op
Address
Code
T1T2T3 1st operand
Address
n
CALL f,mn
if condition is
true)
T1T2T3 2nd operand
Address
m
MC4
MC5
MC6
MC1
Ti
*
Z
1
1
1
0
1
0
0
1
1
0
0
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
T1T2T3 SP-1
T1T2T3 SP-2
PCH
PCL
CCF
T1T2T3 1st Op Code 1st Op
Address Code
UM005001-ZMP0400
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