Z8018x Family
MPU User Manual
253
Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine
Cycle
Instruction
States
Address
Data
RD WR MREQ IORQ M1 HALT ST
AND (IY+ d)
OR (IX + d)
OR (IY+d)
MC4
~MC6
TiTiTi
*
Z
1
1
1
1
1
1
1
XOR (IX + d)
XOR (IY+d)
CP (IX+d)
CP (IY+d)
MC6
MC1
MC2
MC1
MC2
T1T2T3 IX+d
IY+d
DATA
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
1
0
1
T1T2T3 1st Op Code 1st
Address
Op Code
BIT b,g
T1T2T3 2nd Op Code 2nd
Address
Op Code
T1T2T3 1st Op Code 1st
Address
Op Code
BIT b, (HL)
T1T2T3 2nd Op Code 2nd
Address
T1T2T3 HL
T1T2T3 1st Op Code 1st Op
Op Code
MC3
MC1
DATA
0
0
1
1
0
0
1
1
1
0
1
1
1
0
Address Code
MC2
MC3
MC4
MC5
T1T2T3 2nd Op Code 2nd Op
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
1
1
1
1
1
1
1
1
1
Address
Code
BIT b, (IX+d)
BIT b, (IY+d)
T1T2T3 1st operand
Address
d
T1T2T3 3rd Op Code 3rd Op
Address
Code
T1T2T3 IX+ d
DATA
IY+d
UM005001-ZMP0400
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