Z8018x Family
MPU User Manual
252
Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Machine
Instruction
Cycle
States
Address
Data
RD WR MREQ IORQ M1 HALT ST
ADD A,g
ADC A,g
SUB g
SBC A,g
AND g
OR g
MC1
T1T2T3 1st Op Code 1st Op
0
1
1
1
0
1
1
1
0
1
1
1
0
1
Address
*
Code
Z
MC2
Ti
XOR g
CP g
ADD A,m
ADC A,m
SUB m
SBC A,m
AND m
OR m
MC1
MC2
T1T2T3 1st Op Code 1st Op
0
0
1
1
0
0
1
1
0
1
1
1
0
1
Address
Code
T1T2T3 1st operand
Address
m
XOR m
CP m
ADD A, (HL)
ADC A, (HL)
SUB (HL)
SBC A, (HL)
AND HU
MC1
MC2
T1T2T3 1st Op Code 1st Op
0
0
1
1
0
0
1
1
0
1
1
1
0
1
Address
Code
T1T2T3 HL
DATA
OR (HL)
XOR (HL)
CP (HL)
ADD A, (IX+ d) MC1
ADD A, (IY+d)
T1T2T3 1st Op Code 1st Op
Address Code
0
0
1
1
0
0
1
1
0
0
1
1
0
1
ADC A, (IX+d)
ADC A, (IY+d)
MC2
T1T2T3 2nd Op Code 2nd Op
Address
Code
SUB (lX+d)
SUB (IY+d)
SBC A, (IX+ d)
SBC A, (IY+ d) MC3
AND (IX+d)
T1T2T3 1st operand
Address
d
0
1
0
1
1
1
1
UM005001-ZMP0400
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