eZ80L92 MCU
Product Specification
132
The SPI is double-buffered on Read, but not on Write. If a Write is performed during data
transfer, the transfer occurs uninterrupted, and the Write is unsuccessful. This condition
causes the WRITE COLLISION (WCOL) status bit in the SPI_SR register to be set. After
a data byte is shifted, the SPIF flag of the SPI_SR register is set.
In SPI MASTER mode, the SCK pin is an output. It idles High or Low, depending on the
CPOL bit in the SPI_CTL register, until data is written to the shift register. Data transfer is
initiated by writing to the transmit shift register, SPI_TSR. Eight clocks are then generated
to shift the eight bits of transmit data out the MOSI pin while shifting in eight bits of data
on the MISO pin. After transfer, the SCK signal idles.
In SPI SLAVE mode, the start logic receives a logic Low from the SS pin and a clock
input at the SCK pin, and the slave is synchronized to the master. Data from the master is
received serially from the slave MOSI signal and loads the 8-bit shift register. After the 8-
bit shift register is loaded, its data is parallel transferred to the Read buffer. During a Write
cycle data is written into the shift register, then the slave waits for the SPI master to initiate
a data transfer, supply a clock signal, and shift the data out on the slave's MISO signal.
If the CPHA bit in the SPI_CTL register is 0, a transfer begins when SS pin signal goes
Low and the transfer ends when SS goes High after eight clock cycles on SCK. When the
CPHA bit is set to 1, a transfer begins the first time SCK becomes active while SS is Low
and the transfer ends when the SPIF flag gets set.
SPI Flags
Mode Fault
The Mode Fault flag (MODF) indicates that there may be a multimaster conflict for sys-
tem control. The MODF bit is normally cleared to 0 and is only set to 1 when the master
device’s SS pin is pulled Low. When a mode fault is detected, the following occurs:
1. The MODF flag (SPI_SR[4]) is set to 1.
2. The SPI device is disabled by clearing the SPI_EN bit (SPI_CTL[5]) to 0.
3. The MASTER_EN bit (SPI_CTL[4]) is cleared to 0, forcing the device into SLAVE
mode.
4. If the SPI interrupt is enabled by setting IRQ_EN (SPI_CTL[7]) High, an SPI inter-
rupt is generated.
Clearing the Mode Fault flag is performed by reading the SPI Status register. The other
SPI control bits (SPI_EN and MASTER_EN) must be restored to their original states by
user software after the Mode Fault flag is cleared.
PS013015-0316
Serial Peripheral Interface
ZILOG [ ZILOG, INC. ]
