eZ80L92 MCU
Product Specification
135
Table 70. SPI Baud Rate Generator Register—High Byte (SPI_BRG_H = 00B9h)
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset
CPU Access
Note: R/W = Read/Write.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Position
Value
Description
[7:0]
SPI_BRG_H
00h–FFh These bits represent the High byte of the 16-bit Baud Rate
Generator divider value. The complete BRG divisor value is
returned by {SPI_BRG_H, SPI_BRG_L}.
SPI Control Register
This register is used to control and setup the serial peripheral interface. The SPI must be
disabled prior to making any changes to CPHA or CPOL. See Table 71.
Table 71. SPI Control Register (SPI_CTL = 00BAh)
Bit
7
0
6
0
5
0
4
0
3
0
2
1
1
0
0
0
Reset
CPU Access
R/W
R
R/W
R/W
R/W
R/W
R
R
Note: R = Read Only; R/W = Read/Write.
Bit
Position
Value Description
7
0
1
0
0
1
0
1
SPI system interrupt is disabled.
SPI system interrupt is enabled.
Reserved.
IRQ_EN
6
5
SPI is disabled.
SPI_EN
SPI is enabled.
4
When enabled, the SPI operates as a slave.
When enabled, the SPI operates as a master.
MASTER_EN
PS013015-0316
Serial Peripheral Interface
ZILOG [ ZILOG, INC. ]
