eZ80L92 MCU
Product Specification
136
Bit
Position
Value Description
3
0
1
0
1
Master SCK pin idles in a Low (0) state.
Master SCK pin idles in a High (1) state.
CPOL
2
SS must go High after transfer of every byte of data.
SS can remain Low to transfer any number of data bytes.
CPHA
[1:0]
00 Reserved.
SPI Status Register
The SPI Status Read-Only register returns the status of data transmitted using the serial
peripheral interface. Reading the SPI_SR register clears Bits 7, 6, and 4 to a logical 0.
See Table 72.
Table 72. SPI Status Register (SPI_SR = 00BBh)
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset
CPU Access
Note: R = Read Only
R
R
R
R
R
R
R
R
Bit
Position
Value Description
7
0
1
SPI data transfer is not finished.
SPIF
SPI data transfer is finished. If enabled, an interrupt is
generated. This bit flag is cleared to 0 by a Read of the
SPI_SR register.
6
0
1
An SPI write collision is not detected.
WCOL
An SPI write collision is detected. This bit flag is cleared to
0 by a Read of the SPI_SR registers.
5
0
0
1
Reserved.
4
A mode fault (multimaster conflict) is not detected.
MODF
A mode fault (multimaster conflict) is detected. This bit flag
is cleared to 0 by a Read of the SPI_SR register.
[3:0]
0000 Reserved.
PS013015-0316
Serial Peripheral Interface
ZILOG [ ZILOG, INC. ]
