eZ80L92 MCU
Product Specification
116
Bit
Position
Value Description
6
SB
0
1
Do not send a BREAK signal.
Send Break
UART sends continuous zeroes on the transmit output from the
next bit boundary. The transmit data in the transmit shift
register is ignored. After forcing this bit High, the TxD output is
0 only after the bit boundary is reached. Just before forcing
TxD to 0, the transmit FIFO is cleared. Any new data written to
the transmit FIFO during a break should be written only after
the THRE bit of UARTx_LSR register goes High. This new data
is transmitted after the UART recovers from the break. After the
break is removed, the UART recovers from the break for the
next BRG edge.
5
FPE
0
1
Do not force a parity error.
Force a parity error. When this bit and the party enable bit
(PEN) are both 1, an incorrect parity bit is transmitted with the
data byte.
4
EPS
0
1
Use odd parity for transmission. The total number of 1 bits in
the transmit data plus parity bit is odd.
Use even parity for transmission. The total number of 1 bits in
the transmit data plus parity bit is even.
3
PEN
0
1
Parity bit transmit and receive is disabled.
Parity bit transmit and receive is enabled. For transmit, a parity
bit is generated and transmitted with every data character. For
receive, the parity is checked for every incoming data
character.
[2:0]
000–111 UART Character Parameter Selection
CHAR
See Table 61 for a description of the values.
PS013015-0316
Universal Asynchronous Receiver/Transmitter
ZILOG [ ZILOG, INC. ]
