eZ80L92 MCU
Product Specification
115
Bit
Position
Value Description
2
0
1
No effect.
CLRTXF
Clear the transmit FIFO and reset the transmit FIFO pointer.
Valid only if the FIFO is enabled.
1
0
1
No effect.
CLRRXF
Clear the receive FIFO, clear the receive error FIFO, and reset
the receive FIFO pointer. Valid only if the FIFO is enabled.
0
0
1
Transmit and receive FIFOs are disabled. Transmit and receive
buffers are only 1 byte deep.
FIFOEN
Transmit and receive FIFOs are enabled.
UART Line Control Registers
This register is used to control the communication control parameters. See Table 60 and
Table 61.
Table 60. UART Line Control Registers (UART0_LCTL = 00C3h, UART1_LCTL =
00D3h)
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset
CPU Access
Note: R/W = Read/Write.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Position
Value Description
7
0
Access to the UART registers at I/O addresses UARTx_RBR,
UARTx_THR, and UARTx_IER is enabled.
DLAB
1
Access to the Baud Rate Generator registers at I/O addresses
UARTx_BRG_L and UARTx_BRG_H is enabled.
PS013015-0316
Universal Asynchronous Receiver/Transmitter
ZILOG [ ZILOG, INC. ]
