eZ80L92 MCU
Product Specification
114
Table 58. UART Interrupt Status Codes
INSTS Value
Priority
Highest
Second
Third
Interrupt Type
011
010
110
001
000
Receiver Line Status
Receive Data Ready or Trigger Level
Character Time-out
Fourth
Lowest
Transmit Buffer Empty
Modem Status
UART FIFO Control Registers
This register is used to monitor trigger levels, clear FIFO pointers, and enable or disable
the FIFO. The UARTx_FCTL registers share the same I/O addresses as the UARTx_IIR
registers. See Table 59.
Table 59. UART FIFO Control Registers (UART0_FCTL = 00C2h, UART1_FCTL =
00D2h)
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset
CPU Access
Note: W = Write only.
W
W
W
W
W
W
W
W
Bit
Position
Value Description
[7:6]
TRIG
00
01
10
11
Receive FIFO trigger level set to 1. Receive data interrupt is
generated when there is 1 byte in the FIFO. Valid only if FIFO
is enabled.
Receive FIFO trigger level set to 4. Receive data interrupt is
generated when there are 4 bytes in the FIFO. Valid only if
FIFO is enabled.
Receive FIFO trigger level set to 8. Receive data interrupt is
generated when there are 8 bytes in the FIFO. Valid only if
FIFO is enabled.
Receive FIFO trigger level set to 14. Receive data interrupt is
generated when there are 14 bytes in the FIFO. Valid only if
FIFO is enabled.
[5:3]
000 Reserved.
PS013015-0316
Universal Asynchronous Receiver/Transmitter
ZILOG [ ZILOG, INC. ]
