eZ80L92 MCU
Product Specification
113
Bit
Position
Value Description
1
TIE
0
1
Transmit interrupt is disabled.
Transmit interrupt is enabled. Interrupt is generated when the
transmit FIFO/buffer is empty indicating no more bytes
available for transmission.
0
RIE
0
1
Receive interrupt is disabled.
Receive interrupt and receiver time-out interrupt are enabled.
Interrupt is generated if the FIFO/buffer contains data ready to
be read or if the receiver times out.
UART Interrupt Identification Registers
The Read-Only UARTx_IIR register allows you to check whether the FIFO is enabled and
the status of interrupts. These registers share the same I/O addresses as the UARTx_FCTL
registers. See Table 57 and Table 58.
Table 57. UART Interrupt Identification Registers (UART0_IIR = 00C2h, UART1_IIR
= 00D2h)
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
1
Reset
CPU Access
Note: R = Read only.
R
R
R
R
R
R
R
R
Bit
Position
Value
Description
[7:6]
FSTS
00
11
00
FIFO is disabled.
FIFO is enabled.
Reserved
[5:4]
[3:1]
000–110 Interrupt Status Code
INSTS
The code indicated in these three bits is valid only if INTBIT
is 0. If two internal interrupt sources are active and their
respective enable bits are High, only the higher priority
interrupt is seen by the application. The lower-priority
interrupt code is indicated only after the higher-priority
interrupt is serviced. Table 58 lists the interrupt status codes.
0
0
1
There is an active interrupt source within the UART.
There is not an active interrupt source within the UART.
INTBIT
PS013015-0316
Universal Asynchronous Receiver/Transmitter
ZILOG [ ZILOG, INC. ]
