eZ80L92 MCU
Product Specification
119
Bit
Position
Value Description
6
0
Transmit holding register/FIFO is not empty or transmit shift
register is not empty or transmitter is not idle.
TEMT
1
Transmit holding register/FIFO and transmit shift register are
empty; and the transmitter is idle. This bit cannot be set to 1
during the BREAK condition. This bit only becomes 1 after the
BREAK command is removed.
5
0
1
Transmit holding register/FIFO is not empty.
THRE
Transmit holding register/FIFO is empty. This bit cannot be set
to 1 during the BREAK condition. This bit only becomes 1 after
the BREAK command is removed.
4
BI
0
1
Receiver does not detect a BREAK condition. This bit is reset
to 0 when the UARTx_LSR register is read.
Receiver detects a BREAK condition on the receive input line.
This bit is 1 if the duration of BREAK condition on the receive
data is longer than one character transmission time, the time
depends on the programming of the UARTx_LSR register. In
case of FIFO only one null character is loaded into the receiver
FIFO with the framing error. The framing error is revealed to
the eZ80 whenever that particular data is read from the
receiver FIFO.
3
FE
0
1
No framing error detected for character at the top of the FIFO.
This bit is reset to 0 when the UARTx_LSR register is read.
Framing error detected for the character at the top of the FIFO.
This bit is set to 1 when the stop bit following the data/parity bit
is logic 0.
2
PE
0
1
The received character at the top of the FIFO does not contain
a parity error. This bit is reset to 0 when the UARTx_LSR
register is read.
The received character at the top of the FIFO contains a parity
error.
PS013015-0316
Universal Asynchronous Receiver/Transmitter
ZILOG [ ZILOG, INC. ]
