eZ80L92 MCU
Product Specification
120
Bit
Position
Value Description
1
OE
0
The received character at the top of the FIFO does not contain
an overrun error. This bit is reset to 0 when the UARTx_LSR
register is read.
1
Overrun error is detected. If the FIFO is not enabled, this
indicates that the data in the receive buffer register was not
read before the next character was transferred into the receiver
buffer register. If the FIFO is enabled, this indicates the FIFO
was already full when an additional character was received by
the receiver shift register. The character in the receiver shift
register is not put into the receiver FIFO.
0
DR
0
1
This bit is reset to 0 when the UARTx_RBR register is read or
all bytes are read from the receiver FIFO.
Data ready. If the FIFO is not enabled, this bit is set to 1 when
a complete incoming character is transferred into the receiver
buffer register from the receiver shift register. If the FIFO is
enabled, this bit is set to 1 when a character is received and
transferred to the receiver FIFO.
UART Modem Status Registers
This register is used to show the status of the UART signals. See Table 64.
Table 64. UART Modem Status Registers (UART0_MSR = 00C6h, UART1_MSR =
00D6h)
Bit
7
X
R
6
X
R
5
X
R
4
X
R
3
X
R
2
X
R
1
X
R
0
X
R
Reset
CPU Access
Note: R = Read only.
PS013015-0316
Universal Asynchronous Receiver/Transmitter
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