eZ80L92 MCU
Product Specification
110
The UARTx_BRG_L registers share the same address space with the UARTx_RBR and
UARTx_THR registers. The UARTx_BRG_H registers share the same address space with
the UARTx_IER registers. Bit 7 of the associated UART Line Control register
(UARTx_LCTL) must be set to 1 to enable access to the BRG registers.
Note:
Table 52. UART Baud Rate Generator Registers—Low Byte (UART0_BRG_L =
00C0h, UART1_BRG_L = 00D0h)
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
1
0
0
Reset
CPU Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: R = Read only; R/W = Read/Write.
Bit
Position
Value
Description
[7:0]
UARTx_BRG_L
00h–FFh These bits represent the Low byte of the 16-bit Baud Rate
Generator divider value. The complete BRG divisor value
is returned by {UARTx_BRG_H, UARTx_BRG_L}.
Table 53. UART Baud Rate Generator Registers—High Byte (UART0_BRG_H =
00C1h, UART1_BRG_H = 00D1h)
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset
CPU Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: R = Read only; R/W = Read/Write.
Bit
Position
Value
Description
[7:0]
UARTx_BRG_H
00h–FFh These bits represent the High byte of the 16-bit Baud Rate
Generator divider value. The complete BRG divisor value is
returned by {UARTx_BRG_H, UARTx_BRG_L}.
UART Registers
After a RESET, all UART registers are set to their default values. Any Writes to unused
registers or register bits are ignored and Reads return a value of 0. For compatibility with
future revisions, unused bits within a register must be written with a value of 0. Read/
PS013015-0316
Universal Asynchronous Receiver/Transmitter
ZILOG [ ZILOG, INC. ]
