R
QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4000E IOB Output Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup-
ply voltage and junction temperature). For Propagation
Delays, slew-rate = fast unless otherwise noted. Values
apply to all XQ4000E devices unless otherwise noted.
-3
-4
Symbol
Description
Min
Max
Min
Max
Units
Propagation Delays (TTL Output Levels)
T
T
Clock (OK) to pad, fast
-
-
-
-
-
-
-
6.5
9.5
5.5
8.6
4.2
8.1
11.1
-
-
-
-
-
-
-
7.5
11.5
8.0
ns
ns
ns
ns
ns
ns
ns
OKPOF
Clock (OK) to pad, slew-rate limited
Output (O) to pad, fast
OKPOS
T
T
OPF
Output (O) to pad, slew-rate limited
3-state to pad High-Z, slew-rate independent
3-state to pad active and valid, fast
3-state to pad active and valid, slew-rate limited
12.0
10.0
10.0
13.7
OPS
T
TSHZ
TSONF
TSONS
T
T
Propagation Delays (CMOS Output Levels)
T
T
Clock (OK) to pad, fast
-
-
-
-
-
-
-
7.8
11.6
9.7
-
-
-
-
-
-
-
9.5
13.5
10.0
14.0
5.2
ns
ns
ns
ns
ns
ns
ns
OKPOFC
OKPOSC
Clock (OK) to pad, slew-rate limited
Output (O) to pad, fast
T
T
OPFC
Output (O) to pad, slew-rate limited
3-state to pad High-Z, slew-rate independent
3-state to pad active and valid, fast
3-state to pad active and valid, slew-rate limited
13.4
4.3
OPSC
T
TSHZC
TSONFC
TSONSC
T
T
7.6
9.1
11.4
13.1
Setup and Hold Times
T
Output (O) to clock (OK) setup time
Output (O) to clock (OK) hold time
Clock enable (EC) to clock (OK) setup
Clock enable (EC) to clock (OK) hold
4.6
0
-
-
-
-
5.0
0
-
-
-
-
ns
ns
ns
ns
OOK
T
OKO
T
T
3.5
1.2
4.8
1.2
ECOK
OKEC
Clock
T
Clock High
Clock Low
4.0
4.0
-
-
4.5
4.5
-
-
ns
ns
CH
T
CL
Global Set/Reset(3)
T
Delay from GSR net to pad
GSR width
-
11.8
-
15.0
ns
ns
ns
RRO
T
11.5
11.5
-
-
13.0
13.0
-
-
MRW
T
GSR inactive to first active clock (OK) edge
MRO
Notes:
1. Output timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). Slew-rate limited output rise/fall
times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground bounce, see the
“Additional XC4000 Data” section on the Xilinx web site, www.xilinx.com/partinfo/databook.htm.
2. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
3. Timing is based on the XC4005E. For other devices see the XACT timing calculator.
16
www.xilinx.com
DS021 (v2.2) June 25, 2000
1-800-255-7778
Product Specification
XILINX [ XILINX, INC ]
