R
QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4000E CLB Level-Sensitive RAM Timing Characteristics
WRITE
TWC
ADDRESS
TAS
TWP
TAH
WE
TDS
TDH
DATA IN
REQUIRED
READ WITHOUT WRITE
TILO
X,Y OUTPUTS
VALID
VALID
READ, CLOCKING DATA INTO FLIP-FLOP
TICK
TCH
CLOCK
TCKO
XQ,YQ OUTPUTS
VALID (OLD)
VALID (NEW)
READ DURING WRITE
TWP
WRITE ENABLE
TDH
DATA IN
(stable during WE)
TWO
X,Y OUTPUTS
VALID
VALID
NEW
DATA IN
(changing during WE)
OLD
TWO
TDO
VALID
(PREVIOUS)
VALID
(OLD)
VALID
(NEW)
X,Y OUTPUTS
READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP
TWP
WRITE ENABLE
TWCK
TDCK
DATA IN
CLOCK
TCKO
XQ,YQ OUTPUTS
DS021_03_060100
12
www.xilinx.com
DS021 (v2.2) June 25, 2000
1-800-255-7778
Product Specification
XILINX [ XILINX, INC ]
