Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
GTP Transceiver Protocol Jitter Characteristics
For Table 59 through Table 63, the 7 Series FPGAs GTP Transceiver User Guide (UG482) contains recommended settings for
optimal usage of protocol specific characteristics.
Table 59: Gigabit Ethernet Protocol Characteristics
Description
Line Rate (Mb/s)
Min
–
Max
0.24
–
Units
UI
Gigabit Ethernet Transmitter Jitter Generation
Total transmitter jitter (T_TJ)
1250
Gigabit Ethernet Receiver High Frequency Jitter Tolerance
Total receiver jitter tolerance
1250
0.749
UI
Table 60: XAUI Protocol Characteristics
Description
Line Rate (Mb/s)
3125
Min
–
Max
0.35
–
Units
UI
XAUI Transmitter Jitter Generation
Total transmitter jitter (T_TJ)
XAUI Receiver High Frequency Jitter Tolerance
Total receiver jitter tolerance
3125
0.65
UI
(1)
Table 61: PCI Express Protocol Characteristics
Standard
Description
Line Rate (Mb/s)
Min
Max
Units
PCI Express Transmitter Jitter Generation
PCI Express Gen 1
PCI Express Gen 2
Total transmitter jitter
Total transmitter jitter
2500
5000
–
–
0.25
0.25
UI
UI
PCI Express Receiver High Frequency Jitter Tolerance
PCI Express Gen 1
Total receiver jitter tolerance
Receiver inherent timing error
2500
5000
0.65
0.40
0.30
–
–
–
UI
UI
UI
PCI Express Gen 2(2)
Receiver inherent deterministic timing error
Notes:
1. Tested per card electromechanical (CEM) methodology.
2. Using common REFCLK.
Table 62: CEI-6G Protocol Characteristics
Description
Line Rate (Mb/s)
Interface
Min
Max
Units
UI
CEI-6G Transmitter Jitter Generation
Total transmitter jitter(1)
4976–6375
CEI-6G-SR
CEI-6G-SR
–
0.3
–
CEI-6G Receiver High Frequency Jitter Tolerance
Total receiver jitter tolerance(1)
4976–6375
0.6
UI
Notes:
1. Tested at most commonly used line rate of 6250 Mb/s using 390.625 MHz reference clock.
DS181 (v1.25) June 18, 2018
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Product Specification
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