Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 57: GTP Transceiver Transmitter Switching Characteristics
Symbol
Description
Serial data rate range
Condition
Min
Typ
–
Max
FGTPMAX
–
Units
Gb/s
ps
ps
ps
mV
ns
UI
FGTPTX
TRTX
0.500
–
TX rise time
20ꢀ–80ꢀ
80ꢀ–20ꢀ
50
50
–
TFTX
TX fall time
–
–
TLLSKEW
TX lane-to-lane skew(1)
Electrical idle amplitude
Electrical idle transition time
Total Jitter(2)(3)
Deterministic Jitter(2)(3)
Total Jitter(2)(3)
Deterministic Jitter(2)(3)
Total Jitter(2)(3)
Deterministic Jitter(2)(3)
Total Jitter(2)(3)
Deterministic Jitter(2)(3)
Total Jitter(2)(3)
Deterministic Jitter(2)(3)
Total Jitter(2)(3)
Deterministic Jitter(2)(3)
Total Jitter(2)(3)
Deterministic Jitter(2)(3)
Total Jitter(2)(3)
–
500
VTXOOBVDPP
TTXOOBTRANSITION
TJ6.6
–
–
20
–
–
140
–
–
0.30
0.15
0.30
0.15
0.30
0.15
0.30
0.15
0.2
6.6 Gb/s
5.0 Gb/s
DJ6.6
–
–
UI
TJ5.0
–
–
UI
DJ5.0
–
–
UI
TJ4.25
–
–
UI
4.25 Gb/s
3.75 Gb/s
3.20 Gb/s(4)
3.20 Gb/s(5)
2.5 Gb/s(6)
1.25 Gb/s(7)
500 Mb/s
DJ4.25
TJ3.75
–
–
UI
–
–
UI
DJ3.75
TJ3.2
–
–
UI
–
–
UI
DJ3.2
–
–
0.1
UI
TJ3.2L
–
–
0.32
0.16
0.20
0.08
0.15
0.06
0.1
UI
DJ3.2L
TJ2.5
–
–
UI
–
–
UI
DJ2.5
–
–
UI
TJ1.25
–
–
UI
DJ1.25
TJ500
Deterministic Jitter(2)(3)
Total Jitter(2)(3)
Deterministic Jitter(2)(3)
–
–
UI
–
–
UI
DJ500
–
–
0.03
UI
Notes:
1. Using same REFCLK input with TX phase alignment enabled for up to four consecutive transmitters (one fully populated GTP Quad).
2. Using PLL[0/1]_FBDIV = 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.
-12
3. All jitter values are based on a bit-error ratio of 1e
4. PLL frequency at 3.2 GHz and TXOUT_DIV = 2.
5. PLL frequency at 1.6 GHz and TXOUT_DIV = 1.
6. PLL frequency at 2.5 GHz and TXOUT_DIV = 2.
7. PLL frequency at 2.5 GHz and TXOUT_DIV = 4.
.
DS181 (v1.25) June 18, 2018
www.xilinx.com
Product Specification
53