Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 66: Configuration Switching Characteristics (Cont’d)
Speed Grade
-1
Symbol
Description
1.0V
0.95V
-1LI
0.9V
-2LE
Units
-3
-2/-2LE
Internal Configuration Access Port
FICAPCK Internal configuration access port (ICAPE2)
100.00
100.00
100.00
100.00
70.00
MHz, Max
clock frequency
Master/Slave Serial Mode Programming Switching
TDCCK
/
DIN setup/hold
4.00/0.00 4.00/0.00 4.00/0.00 4.00/0.00 5.00/0.00
8.00 8.00 8.00 8.00 9.00
ns, Min
ns, Max
TCCKD
TCCO
DOUT clock to out
SelectMAP Mode Programming Switching
TSMDCCK
/
D[31:00] setup/hold
4.00/0.00 4.00/0.00 4.00/0.00 4.00/0.00 4.50/0.00
4.00/0.00 4.00/0.00 4.00/0.00 4.00/0.00 5.00/0.00
10.00/0.00 10.00/0.00 10.00/0.00 10.00/0.00 12.00/0.00
ns, Min
ns, Min
ns, Min
ns, Max
TSMCCKD
TSMCSCCK
TSMCCKCS
/
CSI_B setup/hold
TSMWCCK
TSMCCKW
/
RDWR_B setup/hold
TSMCKCSO
CSO_B clock to out (330 Ω pull-up resistor
required)
7.00
7.00
7.00
7.00
8.00
TSMCO
D[31:00] clock to out in readback
Readback frequency
8.00
8.00
8.00
8.00
10.00
70.00
ns, Max
FRBCCK
100.00
100.00
100.00
100.00
MHz, Max
Boundary-Scan Port Timing Specifications
TTAPTCK
/
TMS and TDI setup/hold
3.00/2.00 3.00/2.00 3.00/2.00 3.00/2.00 3.00/2.00
ns, Min
TTCKTAP
TTCKTDO
FTCK
TCK falling edge to TDO output
TCK frequency
7.00
7.00
7.00
7.00
8.50
ns, Max
66.00
66.00
66.00
66.00
50.00
MHz, Max
BPI Flash Master Mode Programming Switching
(2)
TBPICCO
A[28:00], RS[1:0], FCS_B, FOE_B, FWE_B,
ADV_B clock to out
8.50
8.50
8.50
8.50
10.00
ns, Max
ns, Min
TBPIDCC
TBPICCD
/
D[15:00] setup/hold
4.00/0.00 4.00/0.00 4.00/0.00 4.00/0.00 4.50/0.00
SPI Flash Master Mode Programming Switching
TSPIDCC
/
D[03:00] setup/hold
3.00/0.00 3.00/0.00 3.00/0.00 3.00/0.00 3.00/0.00
ns, Min
TSPICCD
TSPICCM
MOSI clock to out
FCS_B clock to out
8.00
8.00
8.00
8.00
8.00
8.00
8.00
8.00
9.00
9.00
ns, Max
ns, Max
TSPICCFC
STARTUPE2 Ports
TUSRCCLKO STARTUPE2 USRCCLKO input to CCLK output 0.50/6.00 0.50/6.70 0.50/7.50 0.50/7.50 0.50/7.50
ns,
Min/Max
FCFGMCLK
STARTUPE2 CFGMCLK output frequency
65.00
50
65.00
50
65.00
50
65.00
50
65.00
50
MHz, Typ
ꢀ, Max
FCFGMCLKTOL STARTUPE2 CFGMCLK output frequency
tolerance
DS181 (v1.25) June 18, 2018
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Product Specification
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