Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 34: Regional Clock Buffer Switching Characteristics (BUFR) (Cont’d)
Speed Grade
Symbol
Description
1.0V
-2/-2LE
0.95V
-1LI
0.9V
-2LE
Units
-3
-1
-1Q/-1M
Maximum Frequency
(1)
FMAX_BUFR
Regional clock tree (BUFR)
420.00
375.00
315.00
315.00
315.00
315.00
MHz
Notes:
1. The maximum input frequency to the BUFR and BUFMR is the BUFIO F
frequency.
MAX
Table 35: Horizontal Clock Buffer Switching Characteristics (BUFH)
Speed Grade
Symbol
Description
1.0V
0.95V
-1LI
0.9V
-2LE
0.16
Units
-3
-2/-2LE
-1
-1Q/-1M
TBHCKO_O
TBHCCK_CE
BUFH delay from I to O
CE pin setup and hold
0.10
0.11
0.13
0.13
0.13
ns
ns
/
0.19/0.13 0.22/0.15 0.28/0.21 0.28/0.42 0.28/0.21 0.35/0.25
TBHCKC_CE
Maximum Frequency
FMAX_BUFH Horizontal clock buffer (BUFH)
628.00
628.00
464.00
464.00
464.00
394.00
MHz
Table 36: Duty Cycle Distortion and Clock-Tree Skew
Speed Grade
Symbol
Description
Device
1.0V
-2/-2LE
0.95V
0.9V
-2LE
0.25
Units
-3
-1
-1Q/-1M
-1LI
TDCD_CLK
TCKSKEW
Global clock tree duty-cycle
distortion(1)
All
0.20
0.20
0.20
N/A
0.20
ns
Global clock tree skew(2)
XC7A12T
XC7A15T
XC7A25T
XC7A35T
XC7A50T
XC7A75T
XC7A100T
XC7A200T
XA7A12T
XA7A15T
XA7A25T
XA7A35T
XA7A50T
XA7A75T
XA7A100T
XQ7A50T
XQ7A100T
XQ7A200T
0.26
0.26
0.26
0.26
0.26
0.27
0.27
0.40
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0.14
0.26
0.26
0.26
0.26
0.26
0.33
0.33
0.48
0.26
0.26
0.26
0.26
0.26
0.33
0.33
0.26
0.33
0.48
0.14
0.26
0.26
0.26
0.26
0.26
0.36
0.36
0.54
0.26
0.26
0.26
0.26
0.26
0.36
0.36
0.26
0.36
0.54
0.14
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0.26
0.26
0.26
0.26
0.26
0.36
0.36
0.26
0.36
0.54
0.14
0.26
0.26
0.26
0.26
0.26
0.36
0.36
0.54
N/A
0.33
0.33
0.33
0.33
0.33
0.48
0.48
0.69
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0.14
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
N/A
N/A
N/A
N/A
N/A
N/A
0.26
0.36
0.54
0.14
TDCD_BUFIO I/O clock tree duty cycle distortion All
DS181 (v1.25) June 18, 2018
www.xilinx.com
Product Specification
37
XILINX [ XILINX, INC ]
